As is known in the art, many radar systems use Radio Frequency (RF), Monolithic Microwave Integrated Circuit (MMIC) Power Amplifiers. One such amplifier is shown in FIG. 1. Here, the power amplifier includes a common source connected output Field Effect Transistor (FET) QOUT having its gate fed by an input radio frequency signal (RF IN) to produce an output signal RF OUT at the drain of the QOUT. A bias circuit is provided to produce a reference current Iref which produces a predetermined fixed bias voltage at the gate of the output FET and establishes a predetermined drain current (called the quiescent drain current, Idq, the drain current drawn by the output FET when no RF input is applied to the FET that will result in the output FET producing optimum RF amplification performance when an RF input is applied to the FET).
As is also known, the amount of power dissipated in QOUT is equal to the sum of the DC power applied to the output FET QOUT (the product of the drain voltage VDD and drain current) and the amount of RF power applied to the output FET the QOUT minus the amount of power produced at the output of the output FET QOUT. Thus, even in the absence of RF input signal, there is power dissipated by the output FET (the dissipated power being the product of the drain voltage VDD and quiescent drain current, Idq). For example, for a 1 mm MMIC output FET device biased at Idq=100 mA/mm and with a drain voltage of 20 Volts, the amplifier will dissipate: 1*(0.1)*20=2 Watts. When RF input signal is fully applied, an increase in current QOUT will take place at the same time that output power is delivered out of the circuit. In most cases, this means that there will be a decrease in dissipated power in the output FET QOUT. For example, if the RF driven current (the drain current of FET QOUT) rises by 30% (130 mA) but the output power is 1 Watt for an input of 0.1 Watts, the resulting dissipation in the amplifier will be 0.13 A*20V (DC input power)+0.1 Watt (RF Input Power)−1 Watt (Output Power)=1.7 Watts. The output FET temperature directly correlates to the FET dissipated power. Higher power dissipation causes a higher channel temperature. Higher channel temperatures can either shorten the lifetime of the output FET or can cause immediate failure of the device.
As is also known, in MMIC FET power amplifiers, it is undesirable to turn the drain “on” (conducting) for any appreciable time before applying an RF Input signal as the efficiency of the amplifier is zero for that period of time and the dissipated power on the RF FETs is relatively high. Thus, the gate biasing circuit is provided to set the gate voltage at a predetermined level selected to produce a predetermined quiescent drain current, Idq, density (current per unit FET area) even in the absence of an applied RF input signal so that during application of the RF input signal the RF FET QOUT will have a specific drain current density target.